Figure 9
From: Parallel progressive multiple sequence alignment on reconfigurable meshes
An n × n + 1 n-bit on/off switch. By default, all processing units on the last column (column n + 1) configure {NS,E,W}, and fuse {NSEW} when a signal (i.e. 1) travels through them. All cells on the main anti-diagonal cells of the first n rows and columns fuse {NE,S,W}, cells above the main anti-diagonal fuse {NS,E,W}, and cells below the main anti-diagonal fuse {N,S,EW}. Figure 9(a) shows the r-mesh configuration on a selector bit of 1 (s = 1) and Figure 9(b) shows the r-mesh configuration on a selector bit of 0 (s = 0).